The present invention relates to a microprogram-controlled data processing apparatus and, more particularly, to a 1-bit error detection/correction when microprogram read registers are dispersed.
A microprogram controller of this type includes only one microprogram read register, and has an arrangement, as shown in FIG. 5.
In FIG. 5, reference numeral 1 denotes a control storage device (CS) which holds a microprogram including an ECC (error correcting code) bit and has tri-state I/O pins. The CS 1 comprises a RAM which performs read/write access using a common data line. Reference numeral 2 denotes a 64-bit microprogram read register (RD); 3, an ECC register for holding an 8-bit ECC read out from the CS 1 together with the microprogram; and 4, an error detection/correction circuit for performing an ECC checking operation based on values in the microprogram read register 2 and the ECC register 3 and correcting a 1-bit error. A signal line L1 is a CS bus as a bidirectional data bus among the microprogram read register 2, the ECC register 3, and the CS 1. Reference symbol A denotes a unit comprising the microprogram read register 2, the ECC register 3, and the error detection/correction unit 4.
An operation when a 1-bit error is detected from data read out from the CS 1 by the microprogram read register 2 and the ECC register 3 will be described below with reference to the timing charts of FIGS. 6a to 6d. Data read out from the CS 1 is sent to the microprogram read register 2 and the ECC register 3 (FIGS. 6a and 6b in a period T1). If there is a 1-bit error in readout data (FIGS. 6c and 6d in a period T2), this error is detected upon operation of the error detection/correction circuit 4. In the next clock cycle (period T3), corrected data is stored in the microprogram read register 2 and the ECC register 3. In the next clock cycle (period T4), the corrected data is rewritten in the CS 1.
The conventional microprogram controller described above includes only one microprogram read register 2 in the unit A. Since the clock cycle of the data processing apparatus of this type is extremely shortened to allow high-speed access, when an output from the single microprogram read register is distributed to a plurality of units and is executed, a delay time occurs, and processing cannot be executed in time. Conventionally, portions of the microprogram read register are provided in units other than the unit A, as needed.
However, in this case, when a 1-bit error is detected by the unit A, the microprogram read registers having only some bits in other units must be corrected. In order to correct the microprogram read registers in other units, correction ECC bits must be provided to other units or a new bus for supplying correction data to other units must be arranged, resulting in an increase in a hardware volume and the number of signal lines.